Recently, the operation frequency of semiconductor integrated circuits has been remarkably raised. For instance, in a serial interface, also termed ‘SerDes Interface’ or ‘Advanced Memory Buffer’, realizing high speed serial transfer in a gigabit range, such as DIMM (Dual Inline Memory Module), each channel includes a deserializer and a serializer. The deserializer recovers clock and data, synchronized with data which has been serially received by an input buffer to convert the recovered data into parallel data. The serializer converts the parallel data to be transmitted into serial data. In order to realize synchronized reception of the data among plural channels, frame synchronization patterns are periodically inserted at predetermined positions in the data serially sent from a sending side. The frame synchronization patterns are detected by the reception side to establish frame synchronization among plural channels.
FIG. 3 is a diagram showing the testing configuration of a semiconductor device having a conventional serial interfacing circuit. In a semiconductor device (chip) 10, shown in FIG. 3, N channels from a channel zero to a channel N, where N is an integer not less than 1, are each of the same configuration. Specifically, each channel of the chip includes an input buffer circuit 101, a serial-to-parallel converter (SP) 102, a frame synchronization circuit 103, a skew compensation circuit 107, a parallel-to-serial converter (PS) 104, a selector 106, and an output buffer circuit 105.
The input buffer circuit 101 is supplied with received serial data. The serial-to-parallel converter (SP) 102 converts the received parallel data, input to the input buffer circuit 101, into parallel data. The frame synchronization circuit 103 detects a frame synchronization pattern from parallel data output from the serial-to-parallel converter 102 to take frame synchronization among plural channels and acquires skew information in the channel at the time of the frame synchronization. The skew compensation circuit 107 is supplied with an interrupt enabling signal 110 and interrupt frame 111, generated by a pattern generator (interrupt pattern generator) 109′, and also is supplied with the skew information 112 from the frame synchronization circuit 103 to compensate skew. It is noted that the skew information is the information on lag and lead of the synchronization timing of each channel relative to the frame synchronization timing among plural channels. The parallel-to-serial converter (PS) 104 is supplied with parallel data, skew of which has been compensated by the skew compensation circuit 107, and converts the parallel data into serial data.
The selector 106 is supplied with the serial data from the parallel-to-serial converter 104 and received serial data from the input buffer circuit 101. When the interrupt enabling signal having skew thereof compensated, indicates transmission serial data, the selector 106 selects and outputs the serial data from the parallel-to-serial converter 104 and, when the interrupt enabling signal having skew thereof compensated, indicates a through-frame (output of the input buffer circuit 101), the selector 106 selects and outputs the received serial data output from the input buffer circuit 101. The output buffer circuit 105 serially outputs an output of the selector 106 to a transmission line.
The chip includes, common to the respective channels, a pattern monitor 108 and a pattern generator 109′. The pattern monitor 108 receives frame-synchronized patterns, output from frame synchronization circuits 103 of respective channels, i.e., from channel zero to channel N, to carry out comparison and monitoring as to whether or not the so received patterns coincide with a pattern of expected values. The pattern generator 109′ is adapted for generating the interrupt enabling signal 110 and the interrupt frame 111, based on a command issued from the pattern monitor 108.
It is noted that, in FIG. 3, a clock and data recovery circuit, not shown, for extracting clock and data from the input serial data, is provided between the input buffer circuit 101 and the serial-to-parallel converter 102, and that through-data are supplied to the selector 106 and data sampled and output by the clock and data recovery circuit, not shown, are supplied to the serial-to-parallel converter 102. A clock signal extracted by the clock and data recovery circuit, not shown, is similarly used as a clock signal for conversion in the serial-to-parallel converter 102.
A measurement device 20, such as an LSI tester, supplies a test pattern to the input buffer circuit 101 of the chip 10, as a device under testing (DUT). The measurement device 20 performs a variety of tests of the chip 10, such as pass/fail test (functional tests), AC test, or margin test, by comparing the pattern data, output from an output buffer circuit 105 of the chip 10, with a pattern of expected values.
For confirming whether or not interrupt has been generated, the serial data from the measurement device 20 is supplied to the input buffer circuit 101 of the chip 10. In this chip 10, interrupt data (interrupt frame) is merged into a through-frame (received serial data) by the selector 106 and the so merged data is serially output from the output buffer circuit 105. The measurement device 20 receives the merged data and performs measurement operation such as comparing the merged data received with the pattern of expected values.
Meanwhile, as a test for high-speed data transmission, there has been known a loop-back test for coupling data from a transmit unit to a receiver unit (Patent Document 1).
[Patent Document 1]
JP Patent Kokai Publication No. JP-A-63-39226